A cache-friendly IPv6 LPM with AVX-512 (linearized B+-tree, real BGP benchmarks)
github.com18 points by debugga 3 hours ago
18 points by debugga 3 hours ago
I wonder how this would look like in risc-v vector instructions
Clean-room, portable C++17 implementation of the PlanB IPv6 LPM algorithm.
Includes: - AVX-512 SIMD path + scalar fallback - Wait-free lookups with rebuild-and-swap dynamic FIB - Benchmarks on synthetic data and real RIPE RIS BGP (~254K prefixes)
Interesting result: on real BGP + uniform random lookups, a plain Patricia trie can sometimes match or beat the SIMD tree due to cache locality and early exits.
Would love feedback, especially comparisons with PopTrie / CP-Trie.
The obvious question, I guess: How much faster are you than whatever is in the Linux kernel's FIB? (Although I assume they need RCU overhead and such. I have no idea what it all looks like internally.)
Why detect avx512 in build system instead of using #ifdef ?