Designing a Low Latency 10G Ethernet Core (2023)

ttchisholm.github.io

169 points by picture 4 days ago


Neywiny - 4 days ago

It seems fun to be a high frequency FPGA trader designer. All my FPGA is much lower power consumption so I don't get to play with stuff like gigs of external SRAM or the QDR stuff or whatnot